JAJSP62G December   2002  – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Driver Electrical Characteristics
    6. 8.6  Receiver Electrical Characteristics
    7. 8.7  Driver Switching Characteristics
    8. 8.8  Receiver Switching Characteristics
    9. 8.9  Receiver Equalization Characteristics
    10. 8.10 Power Dissipation
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Test Mode Driver Disable
      2. 10.4.2 Equivalent Input and Output Schematic Diagrams
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Noise Considerations for Equalized Receivers
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.7 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPLH, tPHLDifferential output propagation delay,
low-to-high and high-to-low		RL = 54 Ω, CL = 50 pF, See Figure 9-3SN65HVD2[0,3]61020ns
SN65HVD2[1,4]203260
SN65HVD22160280500
tr, tfDifferential output rise time and fall timeRL = 54 Ω, CL = 50 pF, See Figure 9-3SN65HVD2[0,3]2612ns
SN65HVD2[1,4]204060
SN65HVD22175400600
tPZH, tPHZPropagation delay time,
high-impedance-to-high-level output and
high-level output-to-high-impedance		RE at 0 V, See Figure 9-6SN65HVD2[0,3]40ns
SN65HVD2[1,4]100
SN65HVD22300
tPZL, tPLZPropagation delay time,
high-impedance-to-high-level output and
high-level output-to-high-impedance		RE at 0 V, See Figure 9-7SN65HVD2[0,3]40ns
SN65HVD2[1,4]100
SN65HVD22300
td(standby)Time from an active differential output to standbyRE at VCC, See Figure 9-82µs
td(wake)Wake-up time from standby to an active differential output8µs
tsk(p)Pulse skew | tPLH – tPHL|SN65HVD2[0,3]2ns
SN65HVD2[1,4]6
SN65HVD2250
(1) All typical values are at VCC = 5 V and 25°C