JAJSP62G December   2002  – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Driver Electrical Characteristics
    6. 8.6  Receiver Electrical Characteristics
    7. 8.7  Driver Switching Characteristics
    8. 8.8  Receiver Switching Characteristics
    9. 8.9  Receiver Equalization Characteristics
    10. 8.10 Power Dissipation
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Test Mode Driver Disable
      2. 10.4.2 Equivalent Input and Output Schematic Diagrams
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Noise Considerations for Equalized Receivers
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Driver Electrical Characteristics

over recommended operating conditions (unless otherwise noted).(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIKInput clamp voltageII = –18 mA–1.50.75V
VOOpen-circuit output voltageA or B, No load0VCCV
|VOD(SS)|Steady-state differential output voltageNo load (open circuit)3.34.2VCCV
RL = 54 Ω, See Figure 9-11.82.5
With common-mode loading, See Figure 9-21.8
Δ|VOD(SS)|Change in steady-state differential output voltage between logic statesSee Figure 9-1 and Figure 9-3–0.10.1V
VOC(SS)Steady-state common-mode output voltageSee Figure 9-12.12.52.9V
∆VOC(SS)Change in steady-state common-mode output voltage, VOC(H) – VOC(L)See Figure 9-1 and Figure 9-4–0.10.1V
VOC(PP)Peak-to-peak common-mode output voltage, VOC(MAX) – VOC(MIN)RL = 54 Ω, CL = 50 pF, See Figure 9-1 and Figure 9-40.35V
VOD(RING)Differential output voltage over and under shootRL = 54 Ω, CL = 50 pF, See Figure 9-510%
IIInput currentD, DE–100100µA
IOOutput current with power off.
High impedance state output current.		VO = –7 V to 12 V,
Other input = 0 V		SN65HVD2[0,3]–400500µA
SN65HVD2[1,2,4]–100125
VO = –20 V to 25 V,
Other input = 0 V		SN65HVD2[0,3]–8001000
SN65HVD2[1,2,4]–200250
IOSShort-circuit output currentVO = –20 V to 25 V, See Figure 9-9–250250mA
CODDifferential output capacitance20pF
(1) All typical values are at VCC = 5 V and 25°C.