JAJSP62G December 2002 – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

D|8
- MSOI002K
P|8
- MPDI001B

サーマルパッド・メカニカル・データ

発注情報

9 Parameter Measurement Information

Note:

Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Z_O = 50 Ω (unless otherwise specified).

Figure 9-1 Driver Test Circuit, V_OD and V_OC Without Common-Mode Loading

Figure 9-2 Driver Test Circuit, V_OD With Common-Mode Loading

Figure 9-3 Driver Switching Test Circuit and Waveforms

Figure 9-4 Driver V_OC Test Circuit and Waveforms

V_OD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the V_OD(H) and V_OD(L) steady state values.

Figure 9-5 V_OD(RING) Waveform and Definitions

Figure 9-6 Driver Enable and Disable Test, High Output

Figure 9-7 Driver Enable and Disable Test, Low Output

Figure 9-8 Driver Standby and Wake Test Circuit and Waveforms

Figure 9-9 Driver Short-Circuit Test

Figure 9-10 Receiver DC Parameter Definitions

Figure 9-11 Receiver Switching Test Circuit and Waveforms

Figure 9-12 Receiver Enable Test Circuit and Waveforms, Data Output High

Figure 9-13 Receiver Enable Test Circuit and Waveforms, Data Output Low

Figure 9-14 Receiver Standby and Wake Test Circuit and Waveforms

Figure 9-15 Receiver Active Failsafe Definitions and Waveforms

Figure 9-16 Test Circuit and Waveforms, Transient Overvoltage Test