SLLS933G November   2008  – January 2015 SN65HVD233-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Driver Switching Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Device Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ISO 11898 Compliance of SN65HVD23x Family of 3.3-V CAN Transceivers
        1. 9.3.1.1 Differential Signal
          1. 9.3.1.1.1 Common-Mode Signal
        2. 9.3.1.2 Interoperability Of 3.3-V CAN in 5-V CAN Systems
    4. 9.4 Device Functional Modes
      1. 9.4.1 Function Tables
      2. 9.4.2 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Diagnostic Loopback
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slope Control
        2. 10.2.2.2 Standby
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

pmi_dri_lls557.gifFigure 13. Driver Voltage, Current, and Test Definition
pmi_bus_lls557.gifFigure 14. Bus Logic State Voltage Definitions
pmi_driv_lls557.gifFigure 15. Driver VOD
pmi_dtc_lls557.gif
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 16. Driver Test Circuit and Voltage Waveforms
pmi_rece_lls557.gifFigure 17. Receiver Voltage and Current Definitions
pmi_rectc_lls557.gif
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 18. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT MEASURED
VCANH VCANL R |VID|
–6.1 V –7 V L VOL 900 mV
12 V 11.1 V L 900 mV
–1 V –7 V L 6 V
12 V 6 V L 6 V
–6.5 V –7 V H VOH 500 mV
12 V 11.5 V H 500 mV
–7 V –1 V H 6 V
6 V 12 V H 6 V
Open Open H X
pmi_testc_lls557.gif
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 19. Test Circuit, Transient Overvoltage Test
pmi_tens_lls557.gifFigure 20. Ten(s) Test Circuit and Voltage Waveforms
pmi_vocpp_lls557.gifFigure 21. VOC(pp) Test Circuit and Voltage Waveforms
pmi_tloop_lls557.gifFigure 22. T(loop) Test Circuit and Voltage Waveforms
pmi_tlbk_lls557.gifFigure 23. T(LBK) Test Circuit and Voltage Waveforms
pmi_los_lls557.gifFigure 24. IOS Test Circuit and Waveforms
pmi_comm_lls557.gif
All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 25. Common-Mode Voltage Rejection