JAJSPU8F june   2004  – february 2023 SN65HVD485E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
    1.     6
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Driver
    6. 7.6  Electrical Characteristics: Receiver
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Supply Current
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 Dissipation Ratings
    12. 7.12 Typical Characteristics
      1.      Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Usage in an RS-485 Transceiver
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
        1. 10.1.1.1 Thermal Characteristics of IC Packages
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4 Device Functional Modes

When the driver enable pin (DE) is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A is low, and VOD is negative.

When DE is low, both outputs turn high impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground; thus when left open, the driver is disabled (high impedance) by default. The D pin has an internal pullup resistor to VCC; thus when left open while the driver is enabled, output A turns high and B turns low.

Table 8-1 Driver Function Table
INPUT
D		ENABLE
DE		OUTPUTSFUNCTION
AB
HHHLActively drive bus High
LHLHActively drive bus Low
XLZZDriver disabled
XOPENZZDriver disabled by default
OPENHHLActively drive bus high by default

When the receiver enable pin ( RE) is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold (VIT+) the receiver output (R) turns high. When VID is negative and lower than the negative input threshold (VIT–), the receiver output (R) turns low. If VID is between VIT+ and VIT–, the output is indeterminate.

When RE is logic high or left open, the receiver output is high impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

Table 8-2 Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB		ENABLE
RE		OUTPUT
R		FUNCTION
VIT+ < VIDLHReceive valid bus High
VIT– < VID < VIT+L?Indeterminate bus state
VID < VIT–LLReceive valid bus Low
XHZReceiver disabled
XOPENZReceiver disabled by default
Open-circuit busLHFail-safe high output
Short-circuit busLHFail-safe high output
Idle (terminated) busLHFail-safe high output
GUID-2D5D3D17-C0EF-4450-A6DC-34D38855F158-low.gifFigure 8-1 Equivalent Input and Output Schematic Diagrams