JAJSPZ5 データシート

JAJSPZ5F September 2005 – March 2023 SN65HVD50 , SN65HVD51 , SN65HVD52 , SN65HVD53 , SN65HVD54 , SN65HVD55

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

D|8
- MSOI002K

サーマルパッド・メカニカル・データ

発注情報

7.7 Receiver Switching Characteristics

over recommended operating conditions unless otherwise noted

PARAMETER			TEST CONDITIONS	TYP⁽¹⁾	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output	HVD50, HVD53	V_ID = -1.5 V to 1.5 V, C_L = 15 pF, See Figure 8-9	24	40	ns
t_PLH	Propagation delay time, low-to-high-level output	HVD51, HVD52, HVD54, HVD55		43	55
t_PHL	Propagation delay time, high-to-low-level output	HVD50, HVD53		26	35
t_PHL	Propagation delay time, high-to-low-level output	HVD51, HVD52, HVD54, HVD55		47	60
t_sk(p)	Pulse skew (\|t_PHL - t_PLH\|)	HVD50, HVD53			5
t_sk(p)	Pulse skew (\|t_PHL - t_PLH\|)	HVD51, HVD54			7
t_sk(pp)⁽²⁾	Part-to-part skew	HVD50, HVD53		5
		HVD51, HVD54		6
		HVD52, HVD55		6
t_r	Output signal rise time			2.3	4
t_f	Output signal fall time			2.4	4
t_PHZ	Output disable time from high level		DE at 3 V, C_L = 15 pF See Figure 8-10		17
t_PZH1	Output enable time to high level		DE at 3 V, C_L = 15 pF See Figure 8-10		10
t_PZH2	Propagation delay time, standby-to-high-level output		DE at 0 V, C_L = 15 pF See Figure 8-10		3300
t_PLZ	Output disable time from low level		DE at 3 V, C_L = 15 pF See Figure 8-11		13
t_PZL1	Output enable time to low level		DE at 3 V, C_L = 15 pF See Figure 8-11		10
t_PZL2	Propagation delay time, standby-to-low-level output		DE at 0 V, C_L = 15 pF See Figure 8-11		3300

(1) All typical values are at 25°C and with a 5-V supply

(2) .t_sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.