SLLSEO3 July   2015 SN65HVD63

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Coaxial Interface
      2. 9.3.2 Reference Input
      3. 9.3.3 RS-485 Direction Control
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driver Amplitude Adjust
      2. 10.1.2 Direction Control
      3. 10.1.3 Direction Control Time Constant
      4. 10.1.4 Conversion Between dBm and Peak-to-Peak Voltage
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGT Package
16-Pin VQFN With Exposed Thermal Pad
Top View
SN65HVD63 po_sllseo3.gif

Pin Functions

PIN DESCRIPTION
NAME NO. TYPE
BIAS 10 O Bias voltage output for setting driver output power by external resistors
DIR 5 O Direction control output signal for bus arbitration
DIRSET1 7 — DIRSET1 and DIRSET2: Bits to set the duration of DIR
DIRSET[2:1]: [L:L] = 9.6 kbps; [L:H] = 38.4 kbps; [H:L] = 115 kbps; [H:H] = standby mode
DIRSET2 6 —
GND 8 — Ground
16
RES 9 P Input voltage to adjust driver output power that is set by external resistors from BIAS pin to GND
RXIN 11 I Modulated input signal to the receiver
RXOUT 4 O Digital data bit stream from receiver
SYNCOUT 1 O Open-drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1 and XTAL2
TXIN 2 I Digital data bit stream to driver
TXOUT 12 O Modulated output signal from the driver
VCC 13 P Analog supply voltage for the device
VL 3 P Logic supply voltage for the device
XTAL1 14 I/O I/O pins of the crystal oscillator. Connect a 4 × fC crystal between these pins or connect XTAL1 to an 8.704-MHz clock and connect XTAL2 to GND.
XTAL2 15
EP — — Exposed pad. Connection to ground plane is recommended for best thermal conduction.