JAJSI69A
October 2006 – November 2019
SN65LBC174A-EP
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
ロジック図 (正論理)
4
改訂履歴
5
概要(続き)
5.1
Pin Configuration and Functions
Pin Functions
5.2
Specifications
5.2.1
Absolute Maximum Ratings
5.2.2
ESD Ratings
5.2.3
Recommended Operating Conditions
5.2.4
Thermal Information
5.2.5
Electrical Characteristics
5.2.6
Switching Characteristics
5.2.7
Typical Characteristics
5.3
Parameter Measurement Information
5.4
Detailed Description
5.4.1
Overview
5.4.2
Functional Block Diagram
5.4.3
Feature Description
5.4.4
Device Functional Modes
5.5
Application and Implementation
5.5.1
Application Information
5.5.2
Typical Application
5.5.2.1
Design Requirements
5.5.2.2
Detailed Design Procedure
5.5.2.3
Application Curve
5.6
Power Supply Recommendations
5.7
Layout
5.7.1
Layout Guidelines
5.7.2
Layout Example
6
デバイスおよびドキュメントのサポート
6.1
ドキュメントの更新通知を受け取る方法
6.2
サポート・リソース
6.3
商標
6.4
静電気放電に関する注意事項
6.5
Glossary
7
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DW|20
MPDS173B
DW|16
MSOI003I
サーマルパッド・メカニカル・データ
DW|20
QFND313D
DW|16
QFND313D
発注情報
jajsi69a_oa
jajsi69a_pm
5.3
Parameter Measurement Information
Figure 7.
Test Circuit, V
OD
Without Common-Mode Loading
Figure 8.
Test Circuit, V
OD
With Common-Mode Loading
PRR = 1 MHz, 50% duty cycle, t
r
< 6 ns, t
f
< 6 ns, Z
O
= 50 Ω
Includes probe and jig capacitance.
Figure 9.
V
OC
Test Circuit
PRR = 1 MHz, 50% duty cycle, t
r
< 6 ns, t
f
< 6 ns, Z
O
= 50 Ω
Includes probe and jig capacitance.
Figure 10.
Output Switching Test Circuit and Waveforms
PRR = 1 MHz, 50% duty cycle, t
r
< 6 ns, t
f
< 6 ns, Z
O
= 50 Ω
Includes probe and jig capacitance.
3 V if testing Y output, 0 V if testing Z output.
Figure 11.
Enable Timing Test Circuit and Waveforms, T
PZH
and T
PHZ
PRR = 1 MHz, 50% duty cycle, t
r
< 6 ns, t
f
< 6 ns, Z
O
= 50 Ω
Includes probe and jig capacitance.
3 V if testing Y output, 0 V if testing Z output.
Figure 12.
Enable Timing Test Circuit and Waveforms, T
PZL
and T
PLZ
Figure 13.
Test Circuit, Short-Circuit Output Current
Figure 14.
Test Circuit Waveform, Transient Overvoltage Test
Figure 15.
Equivalent Input and Output Schematic Diagrams