SLLS396 Data sheet

SLLS396G SEPTEMBER 1999 – December 2015 SN65LVDS104 , SN65LVDS105

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9 Detailed Description

9.1 Overview

The SN65LVDS10x are a differential line receiver and a LVTTL input, respectively, connected to four differential signaling (LVDS) line drivers. These devices operate from a single 3.3-V supply. The input signal to the SN65LVDS104 is a differential LVDS signal; this device requires ±100 mV of input signal to determine the correct state of the received signal. The input signal to the SN65LVDS105 is an LVTTL signal. The outputs of both devices are four differential signals complying with the LVDS standard (TIA/EIA-644). The differential output signal operates with a signal level of 350 mV, nominally, at a common-mode voltage of 1.2 V. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

9.2 Functional Block Diagram

SN65LVDS104 SN65LVDS105 logic_dia_01_slls396.gif

Figure 23. Example of Functional Block Diagram (SN65LVDS104)

SN65LVDS104 SN65LVDS105 logic_dia_02_slls396.gif

Figure 24. Example of Functional Block Diagram (SN65LVDS105)

9.3 Feature Description

9.3.1 Fail Safe

A common problem with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. However, TI LVDS receivers handles the open-input circuit situation differently.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 25. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage.

SN65LVDS104 SN65LVDS105 ai_open_cir_lls396.gif

Figure 25. Open-Circuit Fail Safe of the LVDS Receiver

It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in Figure 25. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature.

9.4 Device Functional Modes

Table 2 lists the function tables for the SN65LVDS104 and 105 devices.

Table 2. Function Tables⁽¹⁾

SN65LVDS104				SN65LVDS105
INPUT		OUTPUT		INPUT		OUTPUT
V_ID = V_A - V_B	xEN	xY	xZ	A	ENx	xY	xZ
X	X	Z	Z	L	H	L	H
X	L	Z	Z	H	H	H	L
V_ID ≥ 100 mV	H	H	L	Open	H	L	H
–100 mV < V_ID < 100 mV	H	?	?	X	L	Z	Z
V_ID ≤ –100 mV	H	L	H	X	X	Z	Z

(1) H = high level, L = low level, Z = high impedance, ? = indeterminate, X = don't care

SN65LVDS104 SN65LVDS105 sch_dia_lls396.gif

Figure 26. Equivalent Input and Output Schematic Diagrams

9.4.1 Input Level Translation

An LVDS receiver can be used to receive various other types of logic signals. Figure 27 through Figure 36 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.