JAJSKL8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
The SN65LVDS302 enters the Standby mode when the SN65LVDS302 is not in Shutdown mode but the SubLVDS clock-input common-mode voltage is above 0.9 × VDDLVDS. The CLK input incorporates a pull-up circuit to shift the SubLVDS clock-input common-mode voltage to VDDLVDS in the absence of an input signal. All circuitry except the SubLVDS clock-input Standby monitor is shut down. The SN65LVDS302 also enters Standby mode when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input resistance remains 100 Ω while any input signal on the data inputs D0, D1, and D2 becomes ignored. All outputs holds a static output pattern:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.
The current drawn in Standby mode is very low.