JAJSKL8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time. The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is defined by tPPOS in the transmitter data sheet. For a bit-error-rate target of ≤ 10–12, the measurement duration for tPPOS is ≥ 1012. The SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by tRSKM. The interconnect budget is calculated by Equation 1.
Example: | |
fPCLK(max) | 23 MHz (VGA display resolution, 60 Hz) |
Transmission mode: 2-ChM; tPPOS(SN65LVDS301) | 330 ps |
Target bit error rate | 10–12 |
tRSKM(SN65LVDS302) | 1 / (2 × 15 × fPCLK) – 480 ps = 969 ps |
The interconnect budget for cable skew and ISI must be smaller than the output of Equation 2. |