JAJSKL8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.4 Status Detect and Operating Modes Flow

The SN65LVDS302 switches between the power saving and active modes in the following way:

GUID-BEA66816-64A8-45FE-B5D3-1B473CF1238C-low.gifFigure 8-7 Operating Modes and State Machine Diagram
Table 8-2 Status Detect and Operating Modes Descriptions
MODECHARACTERISTICSCONDITIONS
Shutdown ModeLeast amount of power consumption (most circuitry turned off);
All outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;		RXEN is set low for longer than 10 μs(1)(2)
Standby ModeLow power consumption (Standby monitor circuit active;
PLL is shutdown to conserve power); All outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;		RXEN is high for longer than 10 μs, and both CLK input common-mode VICM(CLK) above 0.9 × VDDLVDS, or CLK input floating(2)
Acquire ModePLL pursues lock; All outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;		RXEN is high; CLK input monitor detected clock input common mode and woke up receiver out of Standby mode
Receive ModeData transfer (normal operation);
receiver deserializes data and provides data on parallel output		RXEN is high and PLL is locked to incoming clock
(1) In Shutdown Mode, all SN65LVDS302 internal switching circuits (for example: PLL, serializer, etc.) are turned off to minimize power consumption. The input stage of any input pin remains active.
(2) Leaving CMOS control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS inputs must be tied to a valid logic level VIL or VIH during Shutdown or Standby Mode. Exceptions are the subLVDS inputs CLK and Dx, which can be left unconnected while not in use.
Table 8-3 Operating Mode Transitions
MODE TRANSITIONUSE CASETRANSITION SPECIFICS
Shutdown → StandbyDrive RXEN high to enable receiver1.RXEN high > 10 μs
2.Receiver enters standby mode
a. R[0:7] = G[0:7] = B[0:7] = VS = HS remain high and DE = PCLK low
b. Receiver activates clock input monitor
Standby → AcquireTransmitter activity detected1.CLK input monitor detects clock input activity
2.Outputs remain static
3.PLL circuit is enabled
Acquire → ReceiveLink is ready to receive data1.PLL is active and approaches lock
2.PLL achieves lock within twakeup
3.D1, D2, or D3 become active depending on LS0 and LS1 selection
4.First Data word was recovered
5.Parallel output bus turns on switching from static output pattern to output first valid data word
Receive → StandbyTransmitter requested to enter Standby mode by input common mode voltage VICM > 0.9 VDDLVDS as when transmitter output clock stops or enters high-impedance state.1.Receiver disables outputs within tsleep
2.RX Input monitor detects VICM > 0.9 VDDLVDS within tsleep
3.R[0:7] = G[0:7] = B[0:7] = VS = HS transition to high and DE = PCLK to low on next falling PLL clock edge
4.PLL shuts down. Clock activity input monitor remains active
Receive and Standby → ShutdownTurn off Receiver1.RXEN pulled low for > tpwrdn
2.R[0:7] = G[0:7] = B[0:7] = VS = HS remain static high or transition to static high and DE = PCLK remain or transition to static low
3.Most IC circuitry is shut down for least power consumption