JAJSKL8E
june 2006 – october 2020
SN65LVDS302
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Input Electrical Characteristics
6.7
Output Electrical Characteristics
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
Device Power Dissipation
Typical Characteristics
7
Parameter Measurement Information
20
7.1
Power Consumption Tests
7.2
Typical IC Power Consumption Test Pattern
7.3
Maximum Power Consumption Test Pattern
7.4
Output Skew Pulse Position and Jitter Performance
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Swap Pin Functionality
8.3.2
Parity Error Detection and Handling
8.4
Device Functional Modes
8.4.1
Deserialization Modes
8.4.1.1
1-Channel Mode
8.4.1.2
2-Channel Mode
8.4.1.3
3-Channel Mode
8.4.2
Powerdown Modes
8.4.2.1
Shutdown Mode
8.4.2.2
Standby Mode
8.4.3
Active Modes
8.4.3.1
Acquire Mode (PLL Approaches Lock)
8.4.3.2
Receive Mode
8.4.4
Status Detect and Operating Modes Flow
9
Application and Implementation
9.1
Application Information
9.1.1
Application Information
9.1.2
Preventing Increased Leakage Currents in Control Inputs
9.1.3
Calculation Example: HVGA Display
9.1.4
How to Determine Interconnect Skew and Jitter Budget
9.1.5
F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
9.1.6
How to Determine the LCD Driver Timing Margin
9.1.7
Typical Application Frequencies
9.2
Typical Applications
9.2.1
VGA Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Power-Up and Power-Down Sequences
9.2.1.3
Application Curves
9.2.2
Dual LCD-Display Application
9.2.2.1
Design Requirements
9.2.2.2
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
12
Device and Documentation Support
12.1
Community Resource
12.2
Trademarks
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZXH|80
MPBGAI9
サーマルパッド・メカニカル・データ
発注情報
jajskl8e_oa
jajskl8e_pm
Figure 7-1
Power Supply Noise Test Set-Up
Figure 7-2
Jitter Budget
Figure 7-3
Output Rise and Fall, Setup and Hold Time
Figure 7-4
SubLVDS Differential Input Rise and Fall Time Defintion
Figure 7-5
Equivalent Input Circuit Design
Figure 7-6
I/O Voltage and Current Definition
Figure 7-7
CMOS Output Test Circuit, Signal and Timing Definition
Figure 7-8
Propagation Delay Input to Output (LS0 = LS1 = 0)
Figure 7-9
Receiver Phase Lock Loop Set Time and Receiver Enable Time
Figure 7-10
Receiver Enable and Disable Glitch Suppression Time
Figure 7-11
Standby Detection