JAJSKL8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
---|---|---|---|---|---|---|
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK– | ||||||
Vthstby | Input voltage common mode threshold to switch between receive and acquire mode and standby mode | RXEN at VDD | 1.3 | 0.9 × VDDLVDS | V | |
VTHL | Low-level differential input voltage threshold | VD0+ – VD0–, VD1+ – VD1–, VD2+ – VD2–, VCLK+ – VCLK– | –40 | mV | ||
VTHH | High-level differential input voltage threshold | VD0+ – VD0–, VD1+ – VD1–, VD2+ – VD2–, VCLK+ – VCLK– | 40 | mV | ||
II+, II– | Input leakage current | VDD = 1.95 V, VI+ = VI–, VI = 0.4 V and VI = 1.5 V | 75 | μA | ||
IIOFF | Power-off input current | VDD = GND; VI = 1.5 V | –75 | μA | ||
RID | Differential input termination resistor value | 78 | 100 | 122 | Ω | |
CIN | Input capacitance | Measured between input terminal and GND | 1 | pF | ||
ΔCIN | Input capacitance variation | Within one signal pair | 0.2 | pF | ||
Between all signals | 1 | |||||
RBBDC | Pull-up resistor for standby detection | 21 | 30 | 39 | kΩ | |
LS0, LS1, CPOL, SWAP, RXEN, F/S | ||||||
VIK | Input clamp voltage | II = –18 mA, VDD = VDD(min) | –1.2 | V | ||
IICMOS | Input current(2) | 0 V ≤ VDD ≤ 1.95 V; VI = {GND, 1.95 V} | 100 | nA | ||
CIN | Input capacitance | 2 | pF | |||
IIH | High-level input current | VIN = 0.7 × VDD | –200 | 200 | nA | |
IIL | Low-level input current | VIN = 0.3 × VDD | –200 | 200 | nA | |
VIH | High-level input voltage | 0.7 × VDD | VDD | V | ||
VIL | Low-level input voltage | 0 | 0.3 × VDD | V |