JAJSKL8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
VthstbyInput voltage common mode threshold to switch between receive and acquire mode and standby modeRXEN at VDD1.30.9 × VDDLVDSV
VTHLLow-level differential input voltage thresholdVD0+ – VD0–, VD1+ – VD1–,
VD2+ – VD2–, VCLK+ – VCLK–		–40mV
VTHHHigh-level differential input voltage thresholdVD0+ – VD0–, VD1+ – VD1–,
VD2+ – VD2–, VCLK+ – VCLK–		40mV
II+, II–Input leakage currentVDD = 1.95 V, VI+ = VI–,
VI = 0.4 V and VI = 1.5 V		75μA
IIOFFPower-off input currentVDD = GND; VI = 1.5 V–75μA
RIDDifferential input termination resistor value78100122Ω
CINInput capacitanceMeasured between input terminal and GND1pF
ΔCINInput capacitance variationWithin one signal pair0.2pF
Between all signals1
RBBDCPull-up resistor for standby detection213039kΩ
LS0, LS1, CPOL, SWAP, RXEN, F/S
VIKInput clamp voltageII = –18 mA, VDD = VDD(min)–1.2V
IICMOSInput current(2)0 V ≤ VDD ≤ 1.95 V;
VI = {GND, 1.95 V}		100nA
CINInput capacitance2pF
IIHHigh-level input currentVIN = 0.7 × VDD–200200nA
IILLow-level input currentVIN = 0.3 × VDD–200200nA
VIHHigh-level input voltage0.7 × VDDVDDV
VILLow-level input voltage00.3 × VDDV
(1) All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
(2) Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level VIH or VOL while power is supplied to VDD.