JAJSF09B February   2015  – April 2015 SN65LVDS93A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Up Sequence
        2. 9.2.2.2 Signal Connectivity
        3. 9.2.2.3 PCB Routing
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Power and Ground Planes
      3. 11.1.3 Traces, Vias, and Other PCB Components
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 商標
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.2 LVDS Output Data

The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts.

Table 2. Pixel Data Assignment

SERIAL CHANNEL DATA BITS 8-BIT 6-BIT 4-BIT
FORMAT-1 FORMAT-2 FORMAT-3 NON-LINEAR STEP SIZE LINEAR STEP SIZE
Y0 D0 R0 R2 R2 R0 R2 VCC
D1 R1 R3 R3 R1 R3 GND
D2 R2 R4 R4 R2 R0 R0
D3 R3 R5 R5 R3 R1 R1
D4 R4 R6 R6 R4 R2 R2
D6 R5 R7 R7 R5 R3 R3
D7 G0 G2 G2 G0 G2 VCC
Y1 D8 G1 G3 G3 G1 G3 GND
D9 G2 G4 G4 G2 G0 G0
D12 G3 G5 G5 G3 G1 G1
D13 G4 G6 G6 G4 G2 G2
D14 G5 G7 G7 G5 G3 G3
D15 B0 B2 B2 B0 B2 VCC
D18 B1 B3 B3 B1 B3 GND
Y2 D19 B2 B4 B4 B2 B0 B0
D20 B3 B5 B5 B3 B1 B1
D21 B4 B6 B6 B4 B2 B2
D22 B5 B7 B7 B5 B3 B3
D24 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC
D25 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC
D26 ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE
Y3 D27 R6 R0 GND GND GND GND
D5 R7 R1 GND GND GND GND
D10 G6 G0 GND GND GND GND
D11 G7 G1 GND GND GND GND
D16 B6 B0 GND GND GND GND
D17 B7 B1 GND GND GND GND
D23 RSVD RSVD GND GND GND GND
CLKOUT CLKIN CLK CLK CLK CLK CLK CLK