JAJSF06A March   2018  – May 2018 SN65LVDS93B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ディスクリートLVDS TXを使用するRGBビデオ・システム
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power
        2. 10.2.2.2 Signal Connectivity
        3. 10.2.2.3 PCB Routing
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VT Input voltage threshold RL = 100 Ω, See Figure 5 IOVCC/2 V
|VOD| Differential steady-state output voltage magnitude 250 450 mV
Δ|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states 1 35 mV
VOC(SS) Steady-state common-mode output voltage See Figure 5
tR/F (Dx, CLKin) = 1 ns		 1.125 1.375 V
VOC(PP) Peak-to-peak common-mode output voltage 35 mV
IIH High-level input current VIH = IOVCC 25 μA
IIL Low-level input current VIL = 0 V ±10 μA
IOS Short-circuit output current VOY = 0 V ±24 mA
VOD = 0 V ±12 mA
IOZ High-impedance state output current VO = 0 V to VCC ±20 μA
Rpdn Input pulldown integrated resistor on all inputs (Dx, CLKSEL, SHTDN, CLKIN) IOVCC = 1.8 V 200 kΩ
IOVCC = 3.3 V 100
IQ Quiescent current Disabled, all inputs at GND;
SHTDN = VIL 		10 100 μA
ICC Supply current (average) SHTDN = VIH, RL = 100 Ω (5 places), grayscale pattern (Figure 6)
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 51.9 mA
I(IOVCC) with IOVCC = 3.3 V 0.4
I(IOVCC) with IOVCC = 1.8 V 0.1
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 7),
VCC = 3.6 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 63.7 mA
I(IOVCC) with IOVCC = 3.3 V 1.3
I(IOVCC) with IOVCC = 1.8 V 0.5
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 7),
fCLK = 85 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 75.1 mA
I(IOVCC) with IOVCC = 3.6 V 1.5
I(IOVCC) with IOVCC = 1.8 V 0.6
CI Input capacitance 2 pF