JAJSF06A March   2018  – May 2018 SN65LVDS93B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ディスクリートLVDS TXを使用するRGBビデオ・システム
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power
        2. 10.2.2.2 Signal Connectivity
        3. 10.2.2.3 PCB Routing
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DGG Package
56-Pin TSSOP
(Top View)

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLKSEL 17 I Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger
(CLKSEL = VIL).
CLKIN 31 I Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKOUTM 40 O Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
CLKOUTP 39 O
D0 51 I Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive).
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND
D1 52
D2 54
D3 55
D4 56
D5 2
D6 3
D7 4
D8 6
D9 7
D10 8
D11 10
D12 11
D13 12
D14 14
D15 15
D16 16
D17 18
D18 19
D19 20
D20 22
D21 23
D22 24
D23 25
D24 27
D25 28
D26 30
D27 50
GND 5, 13, 21, 29, 33, 35, 36, 43, 49, 53 Power Supply(1) Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
IOVCC 1, 26 I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
LVDSVCC 44 3.3-V LVDS output analog supply
PLLVCC 34 3.3-V PLL analog supply
SHTDN 32 I Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation.
VCC 9 Power Supply(1) 3.3-V digital supply voltage
Y0M 48 O Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Y1M 46
Y2M 42
Y0P 47
Y1P 45
Y2P 41
Y3M 38 O Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
Y3P 37
(1) For a multilayer pcb, TI recommends keeping one common GND layer underneath the device and connecting all ground terminals directly to this plane.