SLLS516E August   2002  – July 2015 SN65LVDS100 , SN65LVDS101 , SN65LVDT100 , SN65LVDT101

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Receiver Features
        1. 10.3.1.1 Voltage Range and Common-Mode Range
        2. 10.3.1.2 Sensitivity
        3. 10.3.1.3 Failsafe Considerations
        4. 10.3.1.4 VBB Voltage Reference
        5. 10.3.1.5 Integrated Termination
        6. 10.3.1.6 Receiver Equivalent Schematic
      2. 10.3.2 Driver Features
        1. 10.3.2.1 Signaling Rate, Edge Rate, and Added Jitter
        2. 10.3.2.2 SN65LVDx100 LVDS Output
          1. 10.3.2.2.1 Driver Output Voltage
          2. 10.3.2.2.2 Driver Offset
        3. 10.3.2.3 SN65LVDx101 LVPECL Output
          1. 10.3.2.3.1 Driver Voltage
        4. 10.3.2.4 Driver Equivalent Schematics
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 PECL to LVDS Translation
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Requirements
        3. 11.2.1.3 Application Curve
      2. 11.2.2 LVDS to 3.3-V PECL Translation
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Requirements
        3. 11.2.2.3 Application Curve
      3. 11.2.3 5-V PECL to 3.3-V PECL Translation
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Requirements
        3. 11.2.3.3 Application Curve
      4. 11.2.4 CML to LVDS or 3.3-V PECL Translation
        1. 11.2.4.1 Design Requirements
        2. 11.2.4.2 Detailed Design Requirements
        3. 11.2.4.3 Application Curve
      5. 11.2.5 Single-Ended 3.3-V PECL to LVDS Translation
        1. 11.2.5.1 Design Requirements
        2. 11.2.5.2 Detailed Design Requirements
        3. 11.2.5.3 Application Curve
      6. 11.2.6 Single-Ended CMOS to LVDS Translation
        1. 11.2.6.1 Design Requirements
        2. 11.2.6.2 Detailed Design Requirements
        3. 11.2.6.3 Application Curve
      7. 11.2.7 Single-Ended CMOS to 3.3-V PECL Translation
        1. 11.2.7.1 Design Requirements
        2. 11.2.7.2 Detailed Design Requirements
        3. 11.2.7.3 Application Curve
      8. 11.2.8 Receipt of AC-Coupled Signals
        1. 11.2.8.1 Design Requirements
        2. 11.2.8.2 Detailed Design Requirements
        3. 11.2.8.3 Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs. Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

9 Parameter Measurement Information

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 Vdef_lls516.gifFigure 30. Voltage and Current Definitions

Table 1. Receiver Input Voltage Threshold Test

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE		 RESULTING COMMON-
MODE INPUT VOLTAGE		 OUTPUT(1)
VIA VIB VID VIC
1.25 V 1.15 V 100 mV 1.2 V H
1.15 V 1.25 V –100 mV 1.2 V L
4.0 V 3.9 V 100 mV 3.95 V H
3.9 V 4. 0 V –100 mV 3.95 V L
0.1 V 0.0 V 100 mV 0.05 V H
0.0 V 0.1 V –100 mV 0.05 V L
1.7 V 0.7 V 1000 mV 1.2 V H
0.7 V 1.7 V –1000 mV 1.2 V L
4.0 V 3.0 V 1000 mV 3.5 V H
3.0 V 4.0 V –1000 mV 3.5 V L
1.0 V 0.0 V 1000 mV 0.5 V H
0.0 V 1.0 V –1000 mV 0.5 V L
(1) H = high level, L = low level
SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 diff_lls516.gifFigure 31. SN65LVDx100 Differential Output Voltage (VOD) Test Circuit
SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 ts_lls516.gif

NOTE:

All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the device under test. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 32. Test Circuit and Definitions for the SN65LVDx100 Driver Common-Mode Output Voltage
SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 timewave_lls516.gif

NOTE:

All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the device under test. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 33. Timing Test Circuit and Waveforms
SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 jitter_lls516.gifFigure 34. Driver Jitter Measurement Waveforms
SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 jitset_lls516.gif
A. Source jitter is subtracted from the measured values.
B. TDS JIT3 jitter analysis software installed
Figure 35. Jitter Setup Connections for SN65LVDS100 and SN65LVDS101