SLLSEH7B December   2013  – June 2016 SN65LVPE512

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Case I Fixed Output and Variable Input Trace
      2. 6.8.2 Case II Fixed Input and Variable Output Trace+ 3-m Cable
      3. 6.8.3 Case III Fixed Input and Variable Output Trace (No Cable)
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Eye Diagram and Performance Curves
    2. 7.2 Plot 1 Fixed Output Trace +3-m USB 3 Cable With Variable Input Trace
    3. 7.3 Plot 2 Fixed Input Trace With Variable Output Trace and +3-m USB 3.0 Cable
    4. 7.4 Plot 3 Fixed Input Trace With Variable Output Trace and (No Cable)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Controller- and Connector-Side Pins
      2. 8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing
      3. 8.3.3 Receiver Detection
        1. 8.3.3.1 At Power Up or Reset
        2. 8.3.3.2 During U2, U3 Link State
      4. 8.3.4 Electrical Idle Support
      5. 8.3.5 Signal Control Pin Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

When 5-Gbps SuperSpeed USB signals travel across a PCB or cable, signal integrity degrades due to loss and inter-symbol interference. The SN65LVPE512 recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a high differential voltage. This extends the possible channel length, and enables systems to pass USB 3.0 compliance.

The SN65LVPE512 is located at the Host side, after power up, the SN65LVPE512 periodically performs receiver detection on the TX pair. If it detects a SuperSpeed USB receiver, the RX termination is enabled, and the SN65LVPE512 is ready to re-drive.

The receiver equalizer has three gain settings that are controlled by terminal EQ: 0 dB, 7 dB, and 15 dB. The equalization must be set based on amount of insertion loss in the channel before the SN65LVPE512. Likewise, the output driver supports configuration of De-Emphasis and Output Swing (terminals DE and OS).

8.2 Functional Block Diagram

SN65LVPE512 data_flow_bd_SLLSEH7.gif

8.3 Feature Description

8.3.1 Controller- and Connector-Side Pins

The SN65LVPE512 features a link state machine that makes the device transparent on the USB 3.0 bus while minimizing power. The state machine relies on the system host or device controller to be connected to the pins named Controller. The pins labeled connector must be connected to the USB 3.0 receptacle or captive cable. Multiple SN65LVPE512 devices may be used in series.

8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing

The SN65LVPE512 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal experiences. Level of de-emphasis depends on the length of interconnect and its characteristics. The SN65LVPE512 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in Table 4.

8.3.3 Receiver Detection

8.3.3.1 At Power Up or Reset

After power-up or anytime EN_RXD is toggled, RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX.

If receiver is detected on both channel

  • The TX and RX terminations are switched to ZDIFF_TX, ZDIFF_RX respectively.

If no receiver is detected on one or both channels

  • The transmitter is pulled to Hi-Z
  • The channel is put in low power mode
  • Device attempts to detect Rx termination in 12-ms (typical) intervals until termination is found or device is put in sleep mode

8.3.3.2 During U2, U3 Link State

Rx detection is also performed periodically when link is in U2/U3 states. However in these states during Rx detection, input termination is not automatically disabled before performing Rx.Detect. If termination is found device goes back to its low power state if termination is not found then device disables its input termination and then jumps to power up the RX.Detect state.

8.3.4 Electrical Idle Support

Electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common-mode voltage. 'LVPE512 detects an electrical idle state when RX± voltage at the device pin falls below VRX_LFPS_DIFFp-p minimum. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_LFPS_DIFFp-p max normal operation is restored and output start passing input signal. Electrical idle exit and entry time is specified at < 6 ns.

8.3.5 Signal Control Pin Setting

Table 4. Signal Control Pin Setting

OUTPUT SWING AND EQ CONTROL (at 2.5 GHz)
OSx(1) TRANSISTION BIT AMPLITUDE
(TYP mVpp)		 EQx(1) EQUALIZATION
(dB)
NC (default) 1241 NC (default) 0
0 1105 0 7
1 1324 1 15
OUTPUT DE CONTROL (at 2.5 GHz)
DEx(1) OSx(1) = NC OSx(1) = 0 OSx(1) = 1
NC (default) 0 dB 0 dB 0 dB
0 –3 dB –2 dB –4 dB
1 –5 dB –4 dB –5.6 dB
CONTROL PINS SETTINGS
EN_RXD DEVICE FUNCTION
1 (default) Normal Operation
0 Sleep Mode
(1) Where x = Channel 1 or Channel 2
SN65LVPE512 red_dvr_place_llseh7.gif

NOTE:

For more detailed placement example of redriver, see Parameter Measurement Information.
Figure 33. Redriver Placement Example

8.4 Device Functional Modes

8.4.1 Low Power Modes

Device supports three low power modes as described:

  • Sleep Mode

    • Initiated anytime EN_RXD undergoes a high to low transition and stays low or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode maximum power consumption is 1 mW, entry time is 2 µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100 µs maximum.

  • RX Detect Mode -- When no remote device is connected

    • Anytime 'LVPE512 detects a break in link (that is, when upstream device is disconnected) or after power up fails to find a remote device, 'LVPE512 goes to Rx Detect mode and conserves power by shutting down majority of its internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is < 10 mW (typical) or less than 5% of its normal operating power. This feature is very useful in saving system power in mobile applications like notebook PC where battery life is critical.

    Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device.

  • U2/U3 Mode

    • With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3; in these modes link is in electrical idle state. 'LVPE512 selectively turns off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device automatically reverts to active mode when signal activity (LFPS) is detected.