SCAS530D August   1995  – July 2024 SN74ACT32

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Switching Characteristics
    6. 4.6 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • PW|14
  • DB|14
  • N|14
  • NS|14
サーマルパッド・メカニカル・データ
発注情報

2 Description

The 'ACT32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function Y = A + B or Y = A • B in positive logic.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE (2) BODY SIZE(3)
SN74ACT32 PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.40mm
D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.9mm
DB (SSOP, 14) 6.2mm × 7.8mm 6.2mm × 5.3mm
N (PDIP, 14) 19.3mm × 9.4mm 19.3mm × 6.35mm
NS (SOP, 14) 10.2mm × 7.8mm 10.3mm × 5.3mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74ACT32 Logic Diagram, Each Gate (Positive Logic) Logic Diagram, Each Gate (Positive Logic)