JAJSUA6H June   1998  – April 2024 SN74AHC594

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 3.3 V ± 0.3 V
    7. 5.7  Timing Requirements, VCC = 5 V ± 0.5 V
    8. 5.8  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    9. 5.9  Switching Characteristics, VCC = 5 V ± 0.5 V
    10. 5.10 Noise Characteristics
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support (Analog)
      1. 9.1.1 Related Links
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • DB|16
  • NS|16
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

5.6 Timing Requirements, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
TA = 25°CSN54AHC594(2)SN74AHC594UNIT
MINMAXMINMAXMINMAX
twPulse DurationRCLK or SRCLK high or low5.55.55.5ns
RCLR or SRCLR low555
tsuSetup timeSER before SRCLK↑3.53.53.5ns
SRCLK↑ before RCLK↑(1)88.58.5
SRCLR low before SRCLK↑899
SRCLR high (inactive) before SRCLK↑4.24.84.8
RCLR high (inactive) before RCLK↑4.65.35.3
thHold time,
data after CLK↑		SER after SRCLK↑1.51.51.5ns
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
(2) Product Preview