SCES015M JULY   1995  – June 2015 SN74ALVCH16245

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGG|48
  • DL|48
  • DGV|48
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DGG, DGV, or DL Package
48-Pin TSSOP, TVSOP, or SSOP
Top View
SN74ALVCH16245 po1_ces015.gif
GQL or ZQL Package
56-Pin BGA MICROSTAR JUNIOR
Top View
SN74ALVCH16245 po2_ces015.gif
GRD or ZRD Package
54-Pin BGA MICROSTAR JUNIOR
Top View
SN74ALVCH16245 po3_ces015.gif

Pin Functions

PIN I/O DESCRIPTION
NAME TSSOP, TVSOP, SSOP FBGA (56) FBGA (54)
1A1 47 B5 A6 I/O Transceiver I/O pin
1A2 46 B6 B5 I/O Transceiver I/O pin
1A3 44 C5 B6 I/O Transceiver I/O pin
1A4 43 C6 C5 I/O Transceiver I/O pin
1A5 41 D5 C6 I/O Transceiver I/O pin
1A6 40 D6 D5 I/O Transceiver I/O pin
1A7 38 E5 D6 I/O Transceiver I/O pin
1A8 37 E6 E5 I/O Transceiver I/O pin
2A1 36 F6 E6 I/O Transceiver I/O pin
2A2 35 F5 F5 I/O Transceiver I/O pin
2A3 33 G6 F6 I/O Transceiver I/O pin
2A4 32 G5 G5 I/O Transceiver I/O pin
2A5 30 H6 G6 I/O Transceiver I/O pin
2A6 29 H5 H5 I/O Transceiver I/O pin
2A7 27 J6 H6 I/O Transceiver I/O pin
2A8 26 J5 J6 I/O Transceiver I/O pin
1DIR 1 A1 A3 I Direction control. When high, the signal propagates from A to B. When low, the signal propagates from B to A.
1OE 48 A6 A4 I Output enable
2DIR 24 K1 J3 I Direction control. When high, the signal propagates from A to B. When low, the signal propagates from B to A.
2OE 25 K6 J4 I Output enable
1B1 2 B2 A1 I/O Transceiver I/O pin
1B2 3 B1 B2 I/O Transceiver I/O pin
1B3 5 C2 B1 I/O Transceiver I/O pin
1B4 6 C1 C2 I/O Transceiver I/O pin
1B5 8 D2 C1 I/O Transceiver I/O pin
1B6 9 D1 D2 I/O Transceiver I/O pin
1B7 11 E2 D1 I/O Transceiver I/O pin
1B8 12 E1 E2 I/O Transceiver I/O pin
2B1 13 F1 E1 I/O Transceiver I/O pin
2B2 14 F2 F2 I/O Transceiver I/O pin
2B3 16 G1 F1 I/O Transceiver I/O pin
B4 17 G2 G2 I/O Transceiver I/O pin
2B5 19 H1 G1 I/O Transceiver I/O pin
2B6 20 H2 H2 I/O Transceiver I/O pin
2B7 22 J1 H1 I/O Transceiver I/O pin
2B8 23 J2 J1 I/O Transceiver I/O pin
GND 4,10,15,21,28,34,39,45 B3, B4, D3, D4, G3,G4, J3, J4 D3, D4, E3,E4, F3,F4 — Ground
VCC 7,18,31,42 C3,C4,H3, H4, C3,C4,G3,G4 — Power pin
NC — A2, A3, A4,A5, K2, K3, K4, K5 A2, A5, B3, B4, H3, H4, J2, J5 — No connect

Pin Assignments(1)
(56-Ball GQL or ZQL Package)

1 2 3 4 5 6
A 1DIR NC NC NC NC 1OE
B 1B2 1B1 GND GND 1A1 1A2
C 1B4 1B3 VCC VCC 1A3 1A4
D 1B6 1B5 GND GND 1A5 1A6
E 1B8 1B7 1A7 1A8
F 2B1 2B2 2A2 2A1
G 2B3 2B4 GND GND 2A4 2A3
H 2B5 2B6 VCC VCC 2A6 2A5
J 2B7 2B8 GND GND 2A8 2A7
K 2DIR NC NC NC NC 2OE
(1) NC – No internal connection

Pin Assignments (1)
(54-Ball GRD or ZRD Package)

1 2 3 4 5 6
A 1B1 NC 1DIR 1OE NC 1A1
B 1B3 1B2 NC NC 1A2 1A3
C 1B5 1B4 VCC VCC 1A4 1A5
D 1B7 1B6 GND GND 1A6 1A7
E 2B1 1B8 GND GND 1A8 2A1
F 2B3 2B2 GND GND 2A2 2A3
G 2B5 2B4 VCC VCC 2A4 2A5
H 2B7 2B6 NC NC 2A6 2A7
J 2B8 NC 2DIR 2OE NC 2A8
(1) NC – No internal connection