SCES604J SEPTEMBER   2004  – December 2016 SN74AUP1G00

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 5 pF
    7. 6.7  Switching Characteristics, CL = 10 pF
    8. 6.8  Switching Characteristics, CL = 15 pF
    9. 6.9  Switching Characteristics, CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DPW|5
  • DBV|5
  • DSF|6
  • DCK|5
  • YFP|6
  • DRL|5
  • DRY|6
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.8 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II

2 Applications

  • ATCA Solutions
  • Active Noise Cancellation (ANC)
  • Barcode Scanner
  • Blood Pressure Monitor
  • CPAP Machine
  • Cable Solutions
  • DLP 3D Machine Vision, Hyperspectral Imaging, Optical Networking, and Spectroscopy
  • E-Book
  • Embedded PC
  • Field Transmitter: Temperature or Pressure Sensor
  • Fingerprint Biometrics
  • HVAC: Heating, Ventilating, and Air Conditioning
  • Network-Attached Storage (NAS)
  • Server Motherboard and PSU
  • Software Defined Radio (SDR)
  • TV: High-Definition (HDTV), LCD, and Digital
  • Video Communications System
  • Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card
  • X-ray: Baggage Scanner, Medical, and Dental

3 Description

This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G00DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74AUP1G00DCK SC70 (5) 2.00 mm × 1.25 mm
SN74AUP1G00DRL SOT (5) 1.60 mm × 1.20 mm
SN74AUP1G00DRY SON (6) 1.45 mm × 1.00 mm
SN74AUP1G00DSF SON (6) 1.00 mm × 1.00 mm
SN74AUP1G00YFP DSBGA (6) 1.00 mm × 1.40 mm
SN74AUP1G00YZP DSBGA (5) 1.37 mm × 0.87 mm
SN74AUP1G00DPW X2SON (5) 0.80 mm × 0.80 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74AUP1G00 lo_dgm_ces604.gif