SCES571K JUNE 2004 – June 2014 SN74AUP1G04
PRODUCTION DATA.
The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = A.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The Ioff feature also allows for live insertion.
INPUT A |
INPUT B |
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H | L |
L | H |