SCES578J June   2003  – September 2017 SN74AUP1G14

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: CL = 5 pF
    7. 6.7  Switching Characteristics: CL = 10 pF
    8. 6.8  Switching Characteristics: CL = 15 pF
    9. 6.9  Switching Characteristics: CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 (Propagation Delays, Setup and Hold Times, and Pulse Width)
    2. 7.2 (Enable and Disable Times)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.9 ns Maximum at 3.3 V

2 Applications

  • AV Receivers
  • Smartphones
  • Blu-ray Players and Home Theaters
  • DVD Recorders and Players
  • Desktop or Notebook PCs
  • Embedded PCs
  • GPS: Personal Navigation Devices
  • Mobile Internet Devices
  • Portable Media Players
  • Smoke Detectors
  • Solid State Drive (SSD): Enterprise
  • High-Definition (HDTV)
  • Tablets: Enterprise
  • Audio Docks: Portable
  • DVR and DVS

3 Description

The AUP family is TI's premier solution to the industry's low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G14DBV SOT-23 (5) 2.90 mm x 1.60 mm
SN74AUP1G14DCK SC70 (5) 2.00 mm x 1.25 mm
SN74AUP1G14DRL SOT (5) 1.60 mm x 1.20 mm
SN74AUP1G14DRY SON (6) 1.45 mm x 1.00 mm
SN74AUP1G14DSF SON (6) 1.00 mm x 1.00 mm
SN74AUP1G14DPW X2SON (5) 0.80 mm x 0.80 mm
SN74AUP1G14YFP DSBGA (4) 0.76 mm x 0.76 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)
(DBV, DCK, DRL, DRY, DSF, DPW, and YZP Packages)

SN74AUP1G14 ld_ces578.gif

Logic Diagram (Positive Logic)
(YFP Package)

SN74AUP1G14 ld2_ces578.gif