SCES627D MARCH   2005  – October 2017 SN74AUP1G240

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: CL = 5 pF
    7. 6.7  Switching Characteristics: CL = 10 pF
    8. 6.8  Switching Characteristics: CL = 15 pF
    9. 6.9  Switching Characteristics: CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced 3-State High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. It has a small amount of hysteresis built in allowing for slower or noisy input signals.

The lowered drive produces slower edges and prevents overshoot and undershoot on the outputs. The AUP family of single gate logic makes excellent translators for the new lower voltage microprocessors that typically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories that are still powered by 3.3 V to the lower voltage levels.

The SN74AUP1G240 is essentially an inverter that can be placed into a high-impedance state. In this application, the output is forced to VCC when the SN74AUP1G240's output is disabled, and when the output is enabled, the device performs the function Y = A.

9.2 Typical Application

SN74AUP1G240 sces627_app1.gif Figure 6. Simplified Application Schematic

9.2.1 Design Requirements

SN74AUP1G240 uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.

Pull-up resistor selection is based on leakage current into the Peripheral's input (II) and the high-impedance output of the SN74AUP1G240 (IOZ). See the next section for equations for pull-up resistor (R) selection.

9.2.2 Detailed Design Procedure

  1. Recommended Supply Conditions
  2. Recommended Input Conditions
  3. Recommended Output Conditions
    • Load currents should not exceed the continuous output current maximum rating. See (IO) in the Absolute Maximum Ratings table
    • Outputs should not be pulled above the voltage range applied to any output in the high-impedance or power-off state maximum rating. See (VO) in the Absolute Maximum Ratings table
    • Pull-up resistor (R) selection depends on three primary factors: desired output high voltage (VOH), which is directly related to total leakage current into the SN74AUP1G240 and the peripheral device's input (IL), desired 0 to 90% rising edge time (tr), which is directly related to the parasitic line capacitance (CP), and the maximum current during low output (IOL), which is directly related to the supply value. These three equations govern pull-up resistor selection:
      • R ≤ ( VCC – VOH ) / IL
      • R ≤ tr / ( 2.3 × CP)
      • R ≥ VCC / IOL(max)

9.2.3 Application Curve

SN74AUP1G240 ex_sig_int_ces627.gif Figure 7. Excellent Signal Integrity