SCES603K August 2004 – October 2014 SN74AUP1G34
PRODUCTION DATA.
This single buffer gate operates from 0.8 V to 3.6 V and performs the Boolean function Y = A in positive logic. The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back-flow through the device when it is powered. The Ioff feature also allows for live insertion.
INPUT A |
OUTPUT Y |
---|---|
H | H |
L | L |