JAJSKE9I February   2008  – February 2025 SN74AVC4T774

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics: VCCA = 1.2V ± 0.1V
    7. 5.7  Switching Characteristics: VCCA = 1.5V ± 0.1V
    8. 5.8  Switching Characteristics: VCCA = 1.8V ± 0.15V
    9. 5.9  Switching Characteristics: VCCA = 2.5V ± 0.2V
    10. 5.10 Switching Characteristics: VCCA = 3.3V ± 0.3V
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.1V to 3.6V Power-Supply Range
      2. 7.3.2 Support High-Speed Translation
      3. 7.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 10MHz
  • ZO = 50Ω
  • Δt/ΔV ≤ 1ns/V
SN74AVC4T774 Load Circuit
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
Table 6-1 Load Circuit Parameters
Test Parameter S1
tpd Propagation (delay) time Open
tPZL, tPLZ Enable time, disable time 2 × VCCO
tPZH, tPHZ Enable time, disable time GND
Table 6-2 Load Circuit Conditions
VCCO RL CL VTP
1.2V ± 0.1V 2kΩ 15pF 0.1V
1.5V ± 0.1V 2kΩ 15pF 0.1V
1.8V ± 0.15V 2kΩ 15pF 0.15V
2.5V ± 0.2V 2kΩ 15pF 0.15V
3.3V ± 0.3V 2kΩ 15pF 0.3V
SN74AVC4T774 Propagation Delay
  1. VCCI is the VCC associated with the input port.
  2. VCCO is the VCC associated with the output port.
  3. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1.
  4. tPLH and tPHL are the same as tpd.
  5. The outputs are measured one at a time, with one transition per measurement.
Figure 6-2 Propagation Delay
SN74AVC4T774 Input Transition Rise and Fall Rate
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1.
Figure 6-3 Input Transition Rise and Fall Rate
SN74AVC4T774 Enable Time And Disable Time
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 6-4 Enable Time And Disable Time