JAJSP54D February   2011  – September 2022 SN74GTL2003

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Provides Bidirectional Voltage Translation With No Direction Control Required
      2. 8.3.2 Flow Through Pinout
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional Translation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sizing Pullup Resistors
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Unidirectional Down Translation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Sizing Pullup Resistors
      3. 9.2.3 Unidirectional Up Translation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Sizing Pullup Resistors
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RKS Package,20-Pin VQFN(Top View)
Figure 5-2 PW Package,20-Pin TSSOP(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
D1 18 I/O GTL drain port
D2 17 I/O GTL drain port
D3 16 I/O GTL drain port
D4 15 I/O GTL drain port
D5 14 I/O GTL drain port
D6 13 I/O GTL drain port
D7 12 I/O GTL drain port
D8 11 I/O GTL drain port
DREF 19 — Drain of reference transistor, tie directly to GREF and pull up to reference voltage through a 200-kΩ resistor
GND 1 — Ground
GREF 20 — Gate of reference transistor, tie directly to DREF and pull up to reference voltage through a 200-kΩ resistor
S1 3 I/O LVTTL/TTL source port
S2 4 I/O LVTTL/TTL source port
S3 5 I/O LVTTL/TTL source port
S4 6 I/O LVTTL/TTL source port
S5 7 I/O LVTTL/TTL source port
S6 8 I/O LVTTL/TTL source port
S7 9 I/O LVTTL/TTL source port
S8 10 I/O LVTTL/TTL source port
SREF 2 — Source of reference transistor
(1) I = input, O = output