SCLS751 March   2016 SN74HC595B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI Input voltage -0.5 7 V
IIK Input clamp current(1) VI < 0 -20 mA
IOK Output clamp current (2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
SN74HC595B UNIT
MIN NOM MAX
VCC Supply voltage 2 5 6 V
VIH High-level input voltage VCC = 2 V 1.5 V
VCC = 4.5 V 3.15
VCC = 6 V 4.2
VIL Low-level input voltage VCC = 2 V 0.5 V
VCC = 4.5 V 1.35
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
Δt/Δv Input transition rise or fall time(2) VCC = 2 V 1000 ns
VCC = 4.5 V 500
VCC = 6 V 400
TA Operating free-air temperature –55 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.
(2) If this device is used in the threshold region (from VILmax = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

5.4 Thermal Information

THERMAL METRIC(1) SN74HC595B UNIT
RWN (X1QFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 112 °C/W
RθJCtop Junction-to-case (top) thermal resistance 47.9
RθJB Junction-to-board thermal resistance 72.4
ψJT Junction-to-top characterization parameter 0.6
ψJB Junction-to-board characterization parameter 72.4
RθJCbot Junction-to-case (bottom) thermal resistance 32.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TA = 25°C TA = -55°C to 125°C TA = -40°C to 85°C UNIT
MIN TYP MAX MIN MAX MIN MAX
VOH VI = VIH or VIL IOH = –20 μA 2 V 1.9 1.998 1.9 1.9 V
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
QH′, IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
QA – QH, IOH = –6 mA 3.98 4.3 3.7 3.84
QH′, IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34
QA – QH, IOH = –7.8 mA 5.48 5.8 5.2 5.34
VOL VI = VIH or VIL IOL = 20 μA 2 V 0.002 0.1 0.1 0.1 V
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
QH′, IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
QA – QH, IOL = 6 mA 0.17 0.26 0.4 0.33
QH′, IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
QA – QH, IOL = 7.8 mA 0.15 0.26 0.4 0.33
II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0, QA – QH 6 V ±0.01 ±0.5 ±10 ±5 µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci 2 V to
6 V		 3 10 10 10 pF

5.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
VCC TA = 25°C TA = -55°C to 125°C TA = -40°C to 85°C UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 2 V 6 4.2 5 MHz
4.5 V 31 21 25
6 V 36 25 29
tw Pulse duration SRCLK or RCLK high or low 2 V 80 120 100 ns
4.5 V 16 24 20
6 V 14 20 17
SRCLR low 2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
tsu Set-up time SER before SRCLK↑ 2 V 100 150 125 ns
4.5 V 20 30 25
6 V 17 25 21
SRCLK↑ before RCLK↑(1) 2 V 75 113 94
4.5 V 15 23 19
6 V 13 19 16
SRCLR low before RCLK↑ 2 V 50 75 65
4.5 V 10 15 13
6 V 9 13 11
SRCLR high (inactive) before SRCLK↑ 2 V 50 75 60
4.5 V 10 15 12
6 V 9 13 11
th Hold time, SER after SRCLK↑ 2 V 0 0 0 ns
4.5 V 0 0 0
6 V 0 0 0
(1) This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.

5.7 Switching Characteristics

Over recommended operating free-air temperature range.
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 LOAD CAPACITANCE VCC TA = 25°C TA = -55°C to 125°C TA = -40°C to 85°C UNIT
MIN TYP MAX MIN MAX MIN MAX
fmax 50 pF 2 V 6 26 4.2 5 MHz
4.5 V 31 38 21 25
6 V 36 42 25 29
tpd SRCLK QH′ 50 pF 2 V 50 160 240 200 ns
4.5 V 17 32 48 40
6 V 14 27 41 34
RCLK QA – QH 50 pF 2 V 50 150 225 187
4.5 V 17 30 45 37
6 V 14 26 38 32
tPHL SRCLR QH′ 50 pF 2 V 51 175 261 219 ns
4.5 V 18 35 52 44
6 V 15 30 44 37
ten OE QA – QH 50 pF 2 V 40 150 255 187 ns
4.5 V 15 30 45 37
6 V 13 26 38 32
tdis OE QA – QH 50 pF 2 V 42 200 300 250 ns
4.5 V 23 40 60 50
6 V 20 34 51 43
tt QA – QH 50 pF 2 V 28 60 90 75 ns
4.5 V 8 12 18 15
6 V 6 10 15 13
QH′ 50 pF 2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
tpd RCLK QA – QH 150 pf 2 V 60 200 300 250 ns
4.5 V 22 40 60 50
6 V 19 34 51 43
ten OE QA – QH 150 pf 2 V 70 200 298 250 ns
4.5 V 23 40 60 50
6 V 19 34 51 43
tt QA – QH 150 pf 2 V 45 210 315 265 ns
4.5 V 17 42 63 53
6 V 13 36 53 45
SN74HC595B timing_dgm_cls041.gif Figure 1. Timing Diagram

5.8 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 400 pF

5.9 Typical Characteristics

SN74HC595B SCLS041-ICCVCCtypchar.gif Figure 2. SN74HC595B ICC vs. VCC