JAJSL41C
June 2020 – May 2022
SN74HCS125
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Operating Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS Push-Pull Outputs
8.3.2
CMOS Schmitt-Trigger Inputs
8.3.3
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Power Considerations
9.2.1.2
Input Considerations
9.2.1.3
Output Considerations
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DYY|14
MPSS114B
PW|14
MPDS360
BQA|14
MPQF538A
D|14
MPDS177G
サーマルパッド・メカニカル・データ
BQA|14
QFND686
発注情報
jajsl41c_oa
jajsl41c_pm
9.2.1
Design Requirements
All signals in the system operate at 5 V
Avoid unstable state by not having LOW signals on both inputs
Q output is HIGH when
S
is LOW
Q output remains HIGH until
R
is LOW