JAJSLC3E june   2020  – july 2023 SN74HCS594-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 平衡な CMOS プッシュプル出力
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diode Structure
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 詳細な設計手順
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4 Device Functional Modes

Table 8-1 lists the functional modes of the SN74HCS594-Q1.

Table 8-1 Function Table
INPUTS(1) FUNCTION
SER SRCLK SRCLR RCLK RCLR
X X X X L Output register is cleared
X X L X X Internal shift register is cleared
H/L ↑ H X X SER Data is loaded into first shift bit as H/L, data shifts from bit to bit within the internal shift register
X X H ↑ H Data is transferred from internal shift register to output register
H/L ↑ H ↑ H When SRCLK and RCLK are synchronous, Data is transferred from internal shift register to output register, internal shift register first bit is loaded with SER data H/L and data shifts from bit to bit within internal shift register
X ↓, L, H H X X Internal shift register remains in previous state
X X H ↓, L, H H Output register remains in previous state
(1) H = High Voltage Level, L = Low Voltage Level, X = Do Not Care