JAJSLC3E
june 2020 – july 2023
SN74HCS594-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Characteristics
6.7
Switching Characteristics
6.8
Operating Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
平衡な CMOS プッシュプル出力
8.3.2
CMOS Schmitt-Trigger Inputs
8.3.3
Clamp Diode Structure
8.3.4
Wettable Flanks
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Power Considerations
9.2.1.2
Input Considerations
9.2.1.3
Output Considerations
9.2.2
詳細な設計手順
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
ドキュメントの更新通知を受け取る方法
12.3
サポート・リソース
12.4
Trademarks
12.5
静電気放電に関する注意事項
12.6
用語集
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DYY|16
MPSS115C
PW|16
MPDS361A
BQB|16
MPQF539A
D|16
MPDS178G
サーマルパッド・メカニカル・データ
BQB|16
PPTD365
発注情報
jajslc3e_oa
jajslc3e_pm
11.2
Layout Example
Figure 11-1
Example Layout for the
SN74HCS594-Q1
in the PW Package