JAJSI99F December   2019  – December 2021 SN74HCS595-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9.     15
    10. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Balanced CMOS 3-State Outputs
      2. 8.2.2 Balanced CMOS Push-Pull Outputs
      3. 8.2.3 Latching Logic
      4. 8.2.4 Clamp Diode Structure
      5. 8.2.5 Wettable Flanks
    3. 8.3 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Characteristics

CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
PARAMETER VCC Operating free-air temperature (TA) UNIT
25°C –40°C to 125°C
MIN MAX MIN MAX
tw Pulse duration SRCLK or RCLK high or low 2 V 7 9 ns
4.5 V 7 7
6 V 7 7
SRCLR low 2 V 8 10
4.5 V 7 7
6 V 7 7

tsu
 
Setup time

 SER before SRCLK↑ 2 V 8 13 ns
4.5 V 4 5
6 V 3 4
SRCLK↑ before RCLK↑ 2 V 11 18
4.5 V 5 7
6 V 4 6
SRCLR low before RCLK↑ 2 V 8 13
4.5 V 4 6
6 V 4 5
SRCLR high (inactive) before SRCLK↑ 2 V 8 13
4.5 V 4 6
6 V 4 5

th
 
Hold time

 SER after SRCLK↑ 2 V 0 0 ns
4.5 V 0 0
6 V 0 0