SCLS387M September   1997  – October 2014 SN74LV08A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    7. 7.7  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    8. 7.8  Switching Characteristics, VCC = 5 V ± 0.5 V
    9. 7.9  Noise Characteristics
    10. 7.10 Operating Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • RGY|14
  • DGV|14
  • DB|14
  • PW|14
  • NS|14
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation. The SN74LA08A device performs the Boolean function eq_1_cls387.gif in positive logic.

This device is fully specified for partial-power-down application using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

9.2 Functional Block Diagram

ld_cls387.gifFigure 4. Logic Diagram, Each Gate (Positive Logic)

9.3 Feature Description

  • Wide operating voltage range
    • Operates From 2 V to 5.5 V
  • Allows down voltage translation
    • Inputs accept voltages to 5.5 V
  • Ioff feature
    • Allows voltages on the input or output when VCC is 0 V

9.4 Device Functional Modes

Table 1. Function Table
(Each Gate)

INPUTS OUTPUT
Y
A B
H H H
L X L
X L L