SCLS393Q APRIL   1998  – August 2015 SN74LV123A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 7.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 7.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 7.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 7.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 7.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 7.12 Operating Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power-Down Considerations
        2. 10.2.1.2 Output Pulse Duration
        3. 10.2.1.3 Retriggering Data
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
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発注情報

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever makes more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver.

12.2 Layout Example

SN54LV123A SN74LV123A layoutex1.pngFigure 16. Layout Recommendation
SN54LV123A SN74LV123A layout_scds357.gifFigure 17. Trace Example