JAJSPF3I
april 1998 – march 2023
SN74LV367A
PRODMIX
1
アプリケーション
2
特長
3
概要
4
Revision History
5
Pin Configurations and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics, VCC = 2.5 V ± 0.2 V
6.7
Switching Characteristics, VCC = 3.3 V ± 0.3 V
6.8
Switching Characteristics, VCC = 5 V ± 0.5 V
6.9
Noise Characteristics
6.10
Operating Characteristics
6.11
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Balanced CMOS Push-Pull Outputs
8.3.3
Latching Logic
8.3.4
Partial Power Down (Ioff)
8.3.5
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
PW|16
NS|16
D|16
DGV|16
サーマルパッド・メカニカル・データ
D|16
QFND167D
発注情報
jajspf3i_oa
jajspf3i_pm
6.11
Typical Characteristics
Figure 6-1
TPD vs V
CC