JAJSUR2L May   1999  – June 2024 SN74LV4052A

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information: SN74LV4052A
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Characteristics VCC = 2.5V ± 0.2V
    7. 5.7  Timing Characteristics VCC = 3.3V ± 0.3V
    8. 5.8  Timing Characteristics VCC = 5V ± 0.5V
    9. 5.9  AC Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DB|16
  • PW|16
  • NS|16
  • RGY|16
  • N|16
  • D|16
  • DGV|16
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

SN74LV4052A D or PW Packages, 16-Pin SOIC or TSSOP (Top View)Figure 4-1 D or PW Packages, 16-Pin SOIC or TSSOP (Top View)
SN74LV4052A RGY Package, 16-Pin VQFN With Thermal Pad (Top View)Figure 4-2 RGY Package, 16-Pin VQFN With Thermal Pad (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
2Y0 1 I/O Port 2 channel 0
2Y2 2 I/O Port 2 channel 2
2-COM 3 I/O Port 2 common channel
2Y3 4 I/O Port 2 channel 3
2Y1 5 I/O Port 2 channel 1
INH 6 I Inhibit input
GND 7 — Device ground
GND 8 — Device ground
B 9 I Logic input selector B
A 10 I Logic input selector A
1Y3 11 I/O Port 1 channel 3
1Y0 12 I/O Port 1 channel 0
1-COM 13 I/O Port 1 common channel
1Y1 14 I/O Port 1 channel 1
1Y2 15 I/O Port 1 channel 2
VCC 16 — Device power
(1) I = input, O = output