JAJST70J April 1999 – February 2024 SN74LV4066A
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
1A | 1 | I/O | Input/Output to switch channel 1 |
1B | 2 | I/O | Input/Output to switch channel 1 |
2B | 3 | I/O | Input/Output to switch channel 2 |
2A | 4 | I/O | Input/Output to switch channel 2 |
2C | 5 | I | Control line for channel 2. Switch is ON when control pin is high. |
3C | 6 | I | Control line for channel 3. Switch is ON when control pin is high. |
GND | 7 | — | Ground (0V) reference |
3A | 8 | I/O | Input/Output to switch channel 3 |
3B | 9 | I/O | Input/Output to switch channel 3 |
4B | 10 | I/O | Input/Output to switch channel 4 |
4A | 11 | I/O | Input/Output to switch channel 4 |
4C | 12 | I | Control line for channel 4. Switch is ON when control pin is high. |
1C | 13 | I | Control line for channel 1. Switch is ON when control pin is high. |
VCC | 14 | — | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND. |
Thermal pad | — | It is recommended to tie the pad to GND for the best performance. |