JAJSPD8B december   2022  – april 2023 SN74LV4T08-Q1

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Revision History
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics
   6. 6.6  Switching Characteristics 1.8-V VCC
   7. 6.7  Switching Characteristics 2.5-V VCC
   8. 6.8  Switching Characteristics 3.3-V VCC
   9. 6.9  Switching Characteristics 5.0-V VCC
   10. 6.10 Noise Characteristics
8. 7 Typical Characteristics
9. 8 Parameter Measurement Information
10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
       1. 9.3.1 Balanced CMOS 3-State Outputs
       2. 9.3.2 Clamp Diode Structure
       3. 9.3.3 LVxT Enhanced Input Voltage
          1. 9.3.3.1 Down Translation
          2. 9.3.3.2 Up Translation
       4. 9.3.4 Wettable Flanks
    4. 9.4 Device Functional Modes
11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
       1. 10.2.1 Design Requirements
          1. 10.2.1.1 Power Considerations
          2. 10.2.1.2 Input Considerations
          3. 10.2.1.3 Output Considerations
       2. 10.2.2 Application Curves
12. 11Power Supply Recommendations
13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
14. 13Device and Documentation Support
    1. 13.1 Documentation Support
       1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
15. 14Mechanical, Packaging, and Orderable Information