JAJSQD1
may 2023
SN74LV4T32
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics 1.8-V VCC
6.7
Switching Characteristics 2.5-V VCC
6.8
Switching Characteristics 3.3-V VCC
6.9
Switching Characteristics 5.0-V VCC
6.10
Noise Characteristics
6.11
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Clamp Diode Structure
8.3.3
LVxT Enhanced Input Voltage
8.3.3.1
Down Translation
8.3.3.2
Up Translation
8.3.4
Wettable Flanks
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Power Considerations
9.2.1.2
Input Considerations
9.2.1.3
Output Considerations
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PW|14
MPDS360A
BQA|14
MPQF538A
サーマルパッド・メカニカル・データ
BQA|14
QFND686
発注情報
jajsqd1_oa
10.1.1
Related Documentation
For related documentation, see the following:
Texas Instruments,
CMOS Power Consumption and Cpd Calculation
application note
Texas Instruments,
Designing With Logic
application note
Texas Instruments,
Implications of Slow or Floating CMOS Inputs
application note
Texas Instruments,
Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note