JAJSP10A
August 2022 – November 2022
SN74LV541A-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics, VCC = 2.5 V ± 0.2 V
6.7
Switching Characteristics, VCC = 3.3 V ± 0.3 V
6.8
Switching Characteristics, VCC = 5 V ± 0.5 V
6.9
Noise Characteristics (1)
6.10
Operating Characteristics
6.11
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Partial Power Down (Ioff)
8.3.3
Wettable Flanks
8.3.4
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Power Considerations
9.2.2
Input Considerations
9.2.3
Output Considerations
9.2.4
Detailed Design Procedure
9.2.5
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DGS|20
MPSS137
RKS|20
MPQF266C
サーマルパッド・メカニカル・データ
RKS|20
QFND670A
発注情報
jajsp10a_oa
9.2
Typical Application
Figure 9-1
Input Expansion with Shift Registers