JAJSPD6K
april 1998 – february 2023
SN74LV574A
PRODMIX
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements, VCC = 2.5 V ± 0.2 V
6.7
Timing Requirements, VCC = 3.3 V ± 0.3 V
6.8
Timing Requirements, VCC = 5 V ± 0.5 V
6.9
Switching Characteristics, VCC = 2.5 V ± 0.2 V
6.10
Switching Characteristics, VCC = 3.3 V ± 0.3 V
6.11
Switching Characteristics, VCC = 5 V ± 0.5 V
6.12
Noise Characteristics
6.13
Operating Characteristics
6.14
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Latching Logic
8.3.3
Partial Power Down (Ioff)
8.3.4
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DGV|20
DB|20
NS|20
PW|20
DW|20
RGY|20
サーマルパッド・メカニカル・データ
RGY|20
QFND041R
発注情報
jajspd6k_oa
jajspd6k_pm
6.13
Operating Characteristics
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
TYP
UNIT
C
pd
Power dissipation capacitance
Outputs enabled
C
L
= 50 pF
f = 10 MHz
3.3 V
20.4
pF
5 V
23.8