JAJSOV3G
august 2003 – march 2023
SN74LV595A-Q1
PRODMIX
1
特長
2
アプリケーション
3
説明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements, VCC = 2.5 V ± 0.2 V
6.7
Timing Requirements, VCC = 3.3 V ± 0.3 V
6.8
Timing Requirements, VCC = 5 V ± 0.5 V
6.9
Switching Characteristics, VCC = 2.5 V ± 0.2 V
6.10
Switching Characteristics, VCC = 3.3 V ± 0.3 V
6.11
Switching Characteristics, VCC = 5 V ± 0.5 V
6.12
Timing Diagrams
6.13
Noise Characteristics
6.14
Operating Characteristics
6.15
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Latching Logic
8.3.3
Partial Power Down (Ioff)
8.3.4
Wettable Flanks
8.3.5
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Power Considerations
9.2.2
Input Considerations
9.2.3
Output Considerations
9.2.4
Detailed Design Procedure
9.2.5
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PW|16
MPDS361A
BQB|16
MPQF539A
サーマルパッド・メカニカル・データ
BQB|16
PPTD365
発注情報
jajsov3g_oa
jajsov3g_pm
9.4.2
Layout Example
Figure 9-3
Layout Example for the SN74LV595A-Q1