JAJSQO3 june   2023 SN74LV6T17-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
  8. 7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 平衡な CMOS プッシュプル出力
      2. 9.3.2 Clamp Diode Structure
      3. 9.3.3 CMOS Schmitt-Trigger Inputs
      4. 9.3.4 LVxT Enhanced Input Voltage
        1. 9.3.4.1 Down Translation
        2. 9.3.4.2 Up Translation
      5. 9.3.5 Wettable Flanks
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power Considerations
        2. 10.2.1.2 Input Considerations
        3. 10.2.1.3 Output Considerations
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.4.1 Down Translation

Signals can be translated down using the SN74LV6T17-Q1. The voltage applied at the VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables.

When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state. As shown in Figure 9-2, ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input signals in the LOW state are lower than VIL(MAX).

As shown in Figure 9-3 for example, the standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to match 1.8 V CMOS signals when operating from 1.8-V VCC.

Down Translation Combinations are as follows:

  • 1.8-V VCC – Inputs from 2.5 V, 3.3 V, and 5.0 V
  • 2.5-V VCC – Inputs from 3.3 V and 5.0 V
  • 3.3-V VCC – Inputs from 5.0 V