JAJSQO3 june   2023 SN74LV6T17-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
  8. 7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 平衡な CMOS プッシュプル出力
      2. 9.3.2 Clamp Diode Structure
      3. 9.3.3 CMOS Schmitt-Trigger Inputs
      4. 9.3.4 LVxT Enhanced Input Voltage
        1. 9.3.4.1 Down Translation
        2. 9.3.4.2 Up Translation
      5. 9.3.5 Wettable Flanks
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power Considerations
        2. 10.2.1.2 Input Considerations
        3. 10.2.1.3 Output Considerations
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TA = 25°C -40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
VT+ Positive-going input threshold voltage 1.65 V to 2 V 0.6 1.2 0.5 1.27 V
2.25 V to 2.75 V 0.73 1.39 0.64 1.44
3 V to 3.6 V 0.88 1.59 0.80 1.63
4.5 V to 5.5 V 1.15 2.03 1.1 2.07
VT- Negative-going input threshold voltage 1.65 V to 2 V 0.225 0.685 0.185 0.755 V
2.25 V to 2.75 V 0.295 0.775 0.265 0.805
3 V to 3.6 V 0.385 0.875 0.345 0.895
4.5 V to 5.5 V 0.535 1.075 0.495 1.085
ΔVT Hysteresis (VT+ − VT−) 1.65 V to 2 V 0.35 0.68 0.28 0.8 V
2.25 V to 2.75 V 0.4 0.77 0.33 0.87
3 V to 3.6 V 0.44 0.88 0.38 0.91
4.5 V to 5.5 V 0.53 1.2 0.51 1.4
VOH IOH = -50 uA 1.65 V to 5.5 V VCC-0.1 VCC-0.1 V
IOH = -2 mA 1.65 V to 2 V 1.28 1.7 (1) 1.21
IOH = -3 mA 2.25 V to 2.75 V 2 2.4(1) 1.93
IOH = -5.5 mA 3 V to 3.6 V 2.6 3.08(1) 2.49
IOH = -8 mA 4.5 V to 5.5 V 4.1 4.65(1) 3.95
VOL IOL = 50 uA 1.65 V to 5.5 V 0.1 0.1 V
IOL = 2 mA 1.65 V to 2 V 0.1(1) 0.2 0.25
IOL = 3 mA 2.25 V to 2.75 V 0.1(1) 0.15 0.2
IOL = 5.5 mA 3 V to 3.6 V 0.2(1) 0.2 0.25
IOL = 8 mA 4.5 V to 5.5 V 0.3(1) 0.3 0.35
II VI = 0 V or VCC 0 V to 5.5 V ±0.1 ±1 µA
ICC VI = 0 V or VCC, IO = 0; open on loading 1.65 V to 5.5 V 2 20 µA
ΔICC One input at 0.3 V or 3.4 V, other inputs at 0 or VCC, IO = 0 5.5 V 1.35 1.5 mA
One input at 0.3 V or 1.1 V, other inputs at 0 or VCC, IO = 0 1.8 V 10 20 µA
CI VI = VCC or GND 5 V 4 10 10 pF
CO VO = VCC or GND 5 V 3 pF
CPD(2)(3) No load, F = 1Mhz 5 V 14 pF
(1) Typical value at nearest nominal voltage (1.8 V, 2.5 V, 3.3 V, and 5 V)
(2) CPD is used to determine the dynamic power consumption, per channel.
(3) PD= VCC2xFIx(CPD+ CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage.