JAJSU09 March   2024 SN74LV8T244-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
  9. 8 Feature Description
    1. 8.1 Balanced CMOS 3-State Outputs
    2. 8.2 LVxT Enhanced Input Voltage
    3. 8.3 Clamp Diode Structure
  10. 9 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power Considerations
        2. 10.2.1.2 Input Considerations
        3. 10.2.1.3 Output Considerations
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2. 13.2 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns.

The outputs are measured individually with one input transition per measurement.

TESTS1S2RLCLΔVVCC
tPLH, tPHLOPENOPEN—15pF, 50pF—ALL
tPLZ, tPZLCLOSEDOPEN1kΩ15pF, 50pF0.15V≤ 2.5V
tPHZ, tPZHOPENCLOSED1kΩ15pF, 50pF0.15V≤ 2.5V
tPLZ, tPZLCLOSEDOPEN1kΩ15pF, 50pF0.3V> 2.5V
tPHZ, tPZHOPENCLOSED1kΩ15pF, 50pF0.3V> 2.5V

GUID-EB3CF292-AF1E-41A1-A556-76EDB85F7F6F-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for 3-State Outputs
GUID-20230721-SS0I-8DSF-V0ZP-LHHGHP0QG4NS-low.svg
(3) The greater between tPZL and tPZH is the same as ten.
(4) The greater between tPLZ and tPHZ is the same as tdis.
Figure 6-3 Voltage Waveforms Propagation Delays
GUID-20230721-SS0I-VJQB-BMGP-K0S1JW76FHMX-low.svg
Noise values measured with all other outputs simultaneously switching.
Figure 6-5 Voltage Waveforms, Noise
GUID-535BFE0F-9D7B-4CA6-85AB-D09CD11F52EA-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2 Voltage Waveforms Propagation Delays
GUID-20200713-CA0I-ZTM5-PTJB-WD0LZ8VNG7PG-low.gif
(1) The greater between tr and tf is the same as tt.
Figure 6-4 Voltage Waveforms, Input and Output Transition Times