JAJSP17A december   2022  – april 2023 SN74LV8T245-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics - 1.8-V VCC
    7. 6.7  Switching Characteristics - 2.5-V VCC
    8. 6.8  Switching Characteristics - 3.3-V VCC
    9. 6.9  Switching Characteristics - 5-V VCC
    10. 6.10 Noise Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Clamp Diode Structure
      3. 8.3.3 LVxT Enhanced Input Voltage
        1. 8.3.3.1 Down Translation
        2. 8.3.3.2 Up Translation
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
      1. 9.3.1 Power Considerations
      2. 9.3.2 Input Considerations
      3. 9.3.3 Output Considerations
      4. 9.3.4 Detailed Design Procedure
    4. 9.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RKS|20
  • PW|20
  • DGS|20
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

GUID-6067D196-44B1-43F1-A69E-1CEB5D7FAF12-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 7-1 Load Circuit for 3-State Outputs
GUID-C9DF9E82-1296-42F3-8D48-A817BB167077-low.gif
(1) S1 = CLOSED, S2 = OPEN.
(2) S1 = OPEN, S2 = CLOSED.
(3) The greater between tPZL and tPZH is the same as ten.
(4) The greater between tPLZ and tPHZ is the same as tdis.
Figure 7-3 Voltage Waveforms Propagation Delays
GUID-9730FF14-63B9-450E-8D10-3C05B82DD82E-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2 Voltage Waveforms Propagation Delays
GUID-6166FA54-506A-41C4-8559-71D756BE3E28-low.gif
(1) The greater between tr and tf is the same as tt.
Figure 7-4 Voltage Waveforms, Input and Output Transition Times