DATA SHEET
SN74LVC138A 3-Line to 8-Line Decoders Demultiplexers
1 Features
2 Applications
- LED Displays
- Servers
- White Goods
- Power Infrastructure
- Building Automation
- Factory Automation
3 Description
The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SNx4LVC138A | LCCC (20) | 8.89 mm × 8.89 mm |
| CDIP (16) | 19.56 mm × 6.92 mm | |
| CFP (16) | 10.30 mm × 6.73 mm | |
| SOIC (16) | 9.90 mm × 3.91 mm | |
| SSOP (16) | 6.20 mm × 5.30 mm | |
| TVSOP (16) | 3.60 mm × 4.40 mm | |
| BGA MICROSTAR JUNIOR (20) | 4.00 mm × 3.00 mm | |
| TSSOP (16) | 5.00 mm × 4.40 mm | |
| UQFN (16) | 2.60 mm × 1.80 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
4 Revision History
Changes from V Revision (November 2013) to W Revision
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
- Deleted Ordering Information table; see Packaging Ordering Addendum at the end of the data sheetGo
- Changed RθJA values from: 73 to 86.8 (D), 82 to 100.1 (DB), 120 to 122.1 (DGV), 78 to 84 (ZQN), 108 to 108.9 (PW) Go
- Deleted RθJA values for NS and RGY packagesGo
Changes from U Revision (OCTOBER 2012) to V Revision
- Updated document to new TI data sheet format - no specification changes.Go
- Removed Ordering Information tableGo
- Added ESD warningGo
Changes from T Revision (July 2005) to U Revision
5 Pin Configuration and Functions
SN54LVC138A...RSV PACKAGE
(TOP VIEW)
GQN OR ZQN PACKAGE
(TOP VIEW)
Table 1. Pin Assignments for ZQN (BGA)
| 1 | 2 | 3 | 4 | |
|---|---|---|---|---|
| A | B | A | VCC | Y0 |
| B | C | NC(1) | NC(1) | Y1 |
| C | G2B | G2A | Y3 | Y2 |
| D | G1 | NC(1) | NC(1) | Y4 |
| E | GND | Y7 | Y6 | Y5 |
(1) NC - No internal connection
Pin Functions
| PIN | DESCRIPTION | ||||
|---|---|---|---|---|---|
| NAME | SOIC, SSOP, TVSOP, SO, TSSOP, VQFN, UQFN | LCCC | BGA MICROSTAR JUNIOR |
I/O | |
| A | 1 | 2 | A2 | I | Select input A (least significant bit) |
| B | 2 | 3 | A1 | I | Select input B |
| C | 3 | 4 | B1 | I | Select input C (most significant bit) |
| G2A | 4 | 5 | C2 | I | Active low enable A |
| G2B | 5 | 7 | C1 | I | Active low enable B |
| G1 | 6 | 8 | D1 | I | Active high enable |
| GND | 8 | 10 | E1 | — | Ground |
| NC | — | 1, 11, 16 | B2, B3, D2, D3 | — | No internal connection |
| VCC | 16 | 20 | A3 | — | Supply voltage |
| Y0 | 15 | 19 | A4 | O | Output 0 (least significant bit) |
| Y1 | 14 | 18 | B4 | O | Output 1 |
| Y2 | 13 | 17 | C4 | O | Output 2 |
| Y3 | 12 | 15 | C3 | O | Output 3 |
| Y4 | 11 | 14 | D4 | O | Output 4 |
| Y5 | 10 | 13 | E4 | O | Output 5 |
| Y6 | 9 | 12 | E3 | O | Output 6 |
| Y7 | 7 | 9 | E2 | O | Output 7 (most significant bit) |
