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  • SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

    • SCAS728B October   2003  – September 2014 SN74LVC16374A

      PRODUCTION DATA.  

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  • SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs
  1. 1 Features
  2. 2 Applications
  3. 3 Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

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DATA SHEET

SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

1 Features

  • Member of the Texas Instruments Widebus™ Family
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on
    All Ports (5-V Input and Output Voltages
    With 3.3-V VCC)
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • Servers
  • PCs and Notebooks
  • Network Switches
  • Electronic Points of Sale

Description

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC16374A SSOP (48) 15.80 mm × 7.50 mm
TSSOP (48) 12.50 mm × 6.10 mm
TVSOP (48) 9.70 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

3 Simplified Schematic

ld_cas728.gif

4 Revision History

Changes from A Revision (October 2005) to B Revision

  • Updated document to new TI data sheet standards.Go
  • Deleted Ordering Information table.Go
  • Changed Ioff bullet in Features.Go
  • Added Applications.Go
  • Added Pin Functions table.Go
  • Added Handling Ratings table.Go
  • Changed MAX operating temperature to 125°C in Recommended Operating Conditions. Go
  • Added Thermal Information table.Go
  • Added Typical Characteristics section.Go
  • Added Detailed Description section.Go
  • Added Application and Implementation section.Go
  • Added Power Supply Recommendations and Layout sections.Go

5 Pin Configuration and Functions

po1_cas728.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 1OE I Output Enable 1
2 1Q1 O 1Q1 Output
3 1Q2 O 1Q2 Output
4 GND — Ground Pin
5 1Q3 O 1Q3 Output
6 1Q4 O 1Q4 Output
7 VCC — Power Pin
8 1Q5 O 1Q5 Output
9 1Q6 O 1Q6 Output
10 GND — Ground Pin
11 1Q7 O 1Q7 Output
12 1Q8 O 1Q8 Output
13 2Q1 O 2Q1 Output
14 2Q2 O 2Q2 Output
15 GND — Ground Pin
16 2Q3 O 2Q3 Output
17 2Q4 O 2Q4 Output
18 VCC — Power Pin
19 2Q5 O 2Q5 Output
20 2Q6 O 2Q6 Output
21 GND — Ground Pin
22 2Q7 O 2Q7 Output
23 2Q8 O 2Q8 Output
24 2OE O Output Enable 2
25 2CLK I Clock 2
26 2D8 I 2D8 Input
27 2D7 I 2D7 Input
28 GND — Ground Pin
29 2D6 I 2D6 Input
30 2D5 I 2D5 Input
31 VCC — Power Pin
32 2D4 I 2D4 Input
33 2D3 I 2D3 Input
34 GND — Ground Pin
35 2D2 I 2D2 Input
36 2D1 I 2D1 Input
37 1D8 I 1D8 Input
38 1D7 I 1D7 Input
39 GND — Ground Pin
40 1D6 I 1D6 Input
41 1D5 I 1D5 Input
42 VCC — Power Pin
43 1D4 I 1D4 Input
44 1D3 I 1D3 Input
45 GND — Ground Pin
46 1D2 I 1D2 Input
47 1D1 I 1D1 Input
48 1CLK I Clock 1
po2_cas728.gif

Table 1. Pin Assignments(1)
(56-Ball GQL or ZQL Package)

1 2 3 4 5 6
A 1OE NC NC NC NC 1CLK
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 VCC VCC 1D3 1D4
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 VCC VCC 2D6 2D5
J 2Q7 2Q8 GND GND 2D8 2D7
K 2OE NC NC NC NC 2CLK
(1) NC – No internal connection
po3_cas728.gif

Table 2. Pin Assignments(1)
(54-Ball GRD or ZRD Package)

1 2 3 4 5 6
A 1Q1 NC 1OE 1CLK NC 1D1
B 1Q3 1Q2 NC NC 1D2 1D3
C 1Q5 1Q4 VCC VCC 1D4 1D5
D 1Q7 1Q6 GND GND 1D6 1D7
E 2Q1 1Q8 GND GND 1D8 2D1
F 2Q3 2Q2 GND GND 2D2 2D3
G 2Q5 2Q4 VCC VCC 2D4 2D5
H 2Q7 2Q6 NC NC 2D6 2D7
J 2Q8 NC 2OE 2CLK NC 2D8
(1) NC – No internal connection

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range(2) –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through each VCC or GND ±100 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 0 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 0 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 3.6 V
Data retention only 1.5
VIH High-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC V
VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VIL Low-level input voltage VCC = 1.65 V to 1.95 V 0.35 × VCC V
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
VI Input voltage 0 5.5 V
VO Output voltage High or low state 0 VCC V
3-state 0 5.5
IOH High-level output current VCC = 1.65 V –4 mA
VCC = 2.3 V –8
VCC = 2.7 V –12
VCC = 3 V –24
IOL Low-level output current VCC = 1.65 V 4 mA
VCC = 2.3 V 8
VCC = 2.7 V 12
VCC = 3 V 24
Δt/Δv Input transition rise or fall rate 10 ns/V
TA Operating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004).

6.4 Thermal Information

THERMAL METRIC(1) SN74LVC16374A UNIT
DL DGV DGG
48 PINS
RθJA Junction-to-ambient thermal resistance 68.4 78.4 64.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.7 30.7 17.6
RθJB Junction-to-board thermal resistance 41.0 41.8 31.5
ψJT Junction-to-top characterization parameter 12.3 3.8 1.1
ψJB Junction-to-board characterization parameter 40.4 41.3 31.2
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VOH IOH = –100 μA 1.65 V to 3.6 V VCC – 0.2 V
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.7
IOH = –12 mA 2.7 V 2.2
3 V 2.4
IOH = –24 mA 3 V 2.2
VOL IOL = 100 μA 1.65 V to 3.6 V 0.2 V
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55
II VI = 0 to 5.5 V 3.6 V ±5 μA
Ioff VI or VO = 5.5 V 0 ±10 μA
IOZ VO = 0 to 5.5 V 3.6 V ±10 μA
ICC VI = VCC or GND IO = 0 3.6 V 20 μA
3.6 V ≤ VI ≤ 5.5 V(2) 20
ΔICC One input at VCC – 0.6 V,
Other inputs at VCC or GND		 2.7 V to 3.6 V 500 μA
Ci VI = VCC or GND 3.3 V 5 pF
Co VO = VCC or GND 3.3 V 6.5 pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.

6.6 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 2.7 V VCC = 3.3 V
± 0.3 V		 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 150 150 150 150 MHz
tw Pulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns
tsu Setup time, data before CLK↑ 2.4 1.6 1.9 1.9 ns
th Hold time, data after CLK↑ 0.8 1 1.1 1.9 ns

6.7 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 2.7 V VCC = 3.3 V
± 0.3 V		 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 150 150 150 150 MHz
tpd CLK Q 1 6.5 1 4.3 1 4.9 1.5 4.5 ns
ten OE Q 1 6.7 1 4.7 1 5.3 1.5 4.6 ns
tdis OE Q 1 10.7 1 5 1 6.1 1.5 5.5 ns
tsk(o) 1 1 1 1 ns

6.8 Operating Characteristics

TA = 25°C
PARAMETER TEST
CONDITIONS		 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V UNIT
TYP TYP TYP
Cpd Power dissipation capacitance
per flip-flop		 Outputs enabled f = 10 MHz 47 52 58 pF
Outputs disabled 21 23 24

6.9 Typical Characteristics

D001_SCAS728.gifFigure 1. TPD vs Temperature CLK to Q
D002_SCAS728.gifFigure 2. TPD vs VCC CLK to Q

7 Parameter Measurement Information

pmi_cas728.gifFigure 3. Load Circuit and Voltage Waveforms

 
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